1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product edi88130cs 128kx8 monolithic sram, smd 5962-89598 features n access times of 15*, 17, 20, 25, 35, 45, 55ns n battery back-up operation ? 2v data retention (edi88130lps) n cs 1 , cs 2 & oe functions for bus control n inputs and outputs directly ttl compatible n organized as 128kx8 n commercial, industrial and military temperature ranges n thru-hole and surface mount packages jedec pinout ? 32 pin sidebrazed ceramic dip, 400 mil (package 102) ? 32 pin sidebrazed ceramic dip, 600 mil (package 9) ? 32 lead ceramic soj (package 140) ? 32 pad ceramic quad lcc (package 12) ? 32 pad ceramic lcc (package 141) ? 32 lead ceramic flatpack (package 142) n single +5v ( 10%) supply operation july 2001 rev. 10 pin description i/o 0-7 data inputs/outputs a 0-16 address inputs we write enable cs 1 , cs 2 chip selects oe output enable v cc power (+5v 10%) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a -16 i/o -7 we oe cs 1 cs 2 fig. 1 pin configuration the edi88130cs is a high speed, high performance, 128kx8 bits monolithic static ram. an additional chip enable line provides system memory security during power down in non-battery backed up systems and memory banking in high speed battery backed systems where large mul- tiple pages of memory are required. the edi88130cs has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. a low power version, edi88130lps, offers a 2v data retention function for battery back-up applications. military product is available compliant to mil-prf-38535. *15ns access time is advanced information, contact factory for availability. 32 dip 32 soj 32 clcc 32 flatpack top view 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 cs2 we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a i/o i/o1 i/o2 v ss 32 quad lcc top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 4321 32 31 30 14 15 16 17 18 19 20 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 we a 13 a 8 a 9 a 11 oe a 10 cs 1 i/o 7 a 12 a 14 a 16 nc v cc a 15 cs 2
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs absolute maximum ratings parameter unit voltage on any pin relative to vss -0.2 to 7.0 v operating temperature t a (ambient) industrial -40 to +85 c military -55 to +125 c storage temperature, ceramic -65 to +150 c power dissipation 1.7 w output current 40 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 vcc +0.5 v input low voltage v il -0.5 +0.8 v parameter symbol condition max unit lcc address lines c i v in = vcc or vss, f = 1.0mhz 612pf data lines c o v out = vcc or vss, f = 1.0mhz 814pf these parameters are sampled, not 100% tested. capacitance (t a = +25 c) truth table oe cs 1 cs 2 we mode output power x h x x standby high z icc 2 , icc 3 x x l x standby high z icc 2 , icc 3 h l h h output deselect high z icc 1 l l h h read data out icc 1 x l h l write data in icc 1 note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. input pulse levels v ss to 3.0v input rise and fall times 3ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 w vcc q figure 1 figure 2 255 w 5pf 480 w vcc q 255 w ac test conditions parameter symbol conditions units min typ max input leakage current i li v in = 0v to v cc 5 m a output leakage current i lo v i/o = 0v to v cc 10 m a (15-17ns) 300 ma operating power supply current i cc1 we, cs 1 = v il , i i/o = 0ma, cs 2 = v ih (20ns) 225 ma (25-55ns) 200 ma standby (ttl) power supply current i cc2 cs 1 3 v ih and/or cs 2 v il , (17-55ns) 25 ma v in 3 v ih or v il (15ns) 60 ma cs 1 3 v cc -0.2v and/or cs 2 0.2v cs (17-55ns) 3 10 ma full standby power supply current i cc3 cs (15ns) 15 ma v in 3 vcc -0.2v or v in 0.2v lps 5 ma output low voltage v ol i ol = 8.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v dc characteristics (v cc = 5v, t a = -55 c to +125 c) csoj,dip, flatpack
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs ac characteristics C read cycle (15 to 20ns) (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) symbol 15ns* 17ns 20ns parameter jedec alt. min max min max min max units read cycle time t avav t rc 15 17 20 ns address access time t avqv t aa 15 17 20 ns chip enable access time t e1lqv t acs 15 17 20 ns t e2hqv t acs 15 17 20 ns chip enable to output in low z (1) t e1lqx t clz 555ns t e2hqx t clz 555ns chip disable to output in low z (1) t e1hqz t chz 678ns t e2lqz t chz 678ns output hold from address change t avqx t oh 333ns output enable to output valid t glqv t oe 667ns output enable to output in low z (1) t glqx t olz 000ns output disable to output in high z(1) t ghqz t ohz 568ns chip enable to power up (1) t e1licch t pu 000ns t e2hicch t pu 000ns chip enable to power down (1) t e1hiccl t pd 15 17 20 ns t e2liccl t pd 15 17 20 ns 1. this parameter is guaranteed by design but not tested. * 15ns access time is advanced information, contact factory for availability. ac characteristics C read cycle (25 to 55ns) (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) symbol 25ns 35ns 45ns 55ns parameter jedec alt. min max min max min max min max units read cycle time t avav t rc 25 35 45 55 ns address access time t avqv t aa 25 35 45 55 ns chip enable access time t e1lqv t acs 25 35 45 55 ns chip enable access time t e2hqv t acs 25 35 45 55 ns chip enable to output in low z (1) t e1lqx t clz 5555ns t e2hqx t clz 5555ns chip disable to output in low z (1) t e1hqz t chz 10 15 20 20 ns t e2lqz t chz 10 15 20 20 ns output hold from address change t avqx t oh 0000ns output enable to output valid t glqv t oe 10 15 20 25 ns output enable to output in low z (1) t glqx t olz 0000ns output disable to output in high z(1) t ghqz t ohz 10 15 20 20 ns chip enable to power up (1) t e1licch t pu 0000ns t e2hicch t pu 0000ns chip enable to power down (1) t e1hiccl t pd 25 35 45 55 ns t e2liccl t pd 25 35 45 55 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs ac characteristics C write cycle (15 to 20ns) (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 15ns* 17ns 20ns parameter jedec alt. min max min max min max units write cycle time t avav t wc 15 17 20 ns chip enable to end of write t e1lwh t cw 12 13 15 ns t e1le1h t cw 12 13 15 ns t e2hwh t cw 12 13 15 ns t e2he2l t cw 12 13 15 ns address setup time t avwl t as 000ns t ave1l t as 000ns t ave2h t as 000ns address valid to end of write t avwh t aw 12 13 15 ns write pulse width t wlwh t wp 12 13 15 ns t wle1h t wp 12 13 15 ns t wle2l t wp 12 13 15 ns write recovery time t whax t wr 000ns t e1hax t wr 000ns t e2lax t wr 000ns data hold time t whdx t dh 000ns t e1hdx t dh 000ns t e2ldx t dh 000ns write to output in high z (1) t wlqz t whz 0 70808 ns data to write time t dvwh t dw 7810ns t dve1h t dw 7810ns t dve2l t dw 7810ns output active from end of write (1) t whqx t wlz 333ns 1. this parameter is guaranteed by design but not tested. ac characteristics C write cycle (25 to 55ns) (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 25ns 35ns 45ns 55ns parameter jedec alt. min max min max min max min max units write cycle time t avav t wc 25 35 45 55 ns chip enable to end of write t e1lwh t cw 20 25 35 45 ns t e1le1h t cw 16 20 25 40 ns t e2hwh t cw 16 20 25 40 ns t e2he2l t cw 16 20 25 40 ns address setup time t avwl t as 00 00ns t ave1l t as 00 00ns t ave2h t as 00 00ns address valid to end of write t avwh t aw 20 25 35 45 ns t aveh t aw 20 25 35 45 ns write pulse width t wlwh t wp 20 30 30 35 ns t wle1h t wp 20 30 30 35 ns t wle2l t wp 20 30 30 35 ns write recovery time t whax t wr 00 55ns t e1hax t wr 00 55ns t e2lax t wr 00 55ns data hold time t whdx t dh 00 00ns t e1hdx t dh 00 00ns t e2ldx t dh 00 00ns write to output in high z (1) t wlqz t whz 0 10 0 13 0 15 0 20 ns data to write time t dvwh t dw 15 20 20 25 ns t dve1h t dw 15 20 20 25 ns t dve2l t dw 15 20 20 25 ns output active from end of write (1) t whqx t wlz 33 33ns 1. this parameter is guaranteed by design but not tested.
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs address data i/o read cycle 1 (we high; oe, cs low) t avqx t avqv t avav data 2 address 1 address 2 data 1 read cycle 2 (cs 1 and/or cs 2 controlled, we high) address data i/o t avqv t e1lqv t glqv t e1lqx t glqx t avav t e1hqz t ghqz oe icc cs 1 t e1licch t e1hiccl cs 2 t e2hicch t e2liccl t e2hqv t e2hqx fig. 2 timing waveform - read cycles fig. 3 write cycle 1 ws32k32-xhx fig. 4 write cycles 2 address data in write cycle 1 - late write, we controlled t avwh t wlwh t whax t e2hwh t dvwh t wlqz t whqx t avwl t whdx t avav t e1lwh cs 1 data out we cs 2 address data i/o write cycle 2 - early write, cs 1 controlled t e1le1h t e1hax t dve1h t e1hdx t avav cs 1 we cs 2 t ave1l address data i/o write cycle 3 - early write, cs 2 controlled t e2he2l t e2lax t dve2l t e2ldx t avav cs 1 we cs 2 t ave2h write cycles 3
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs characteristic sym conditions min typ max units low power version only data retention voltage v dd v dd = 2.0v 2 C C v data retention quiescent current i ccdr cs 1 3 v dd -0.2v and/or cs 2 3 v ss +0.2v C 0.5 2 ma chip disable to data retention time (1) t cdr v in 3 v dd -0.2v 0 C C ns operation recovery time (1) t r or v in 0.2v t avav *C Cns note: 1. parameter guaranteed by design, but not tested. * read cycle time data retention characteristics (edi88130lps only) (t a = -55 c to +125 c) ws32k32-xhx fig. 5 data retention - cs 1 controlled data retention, cs 2 controlled data retention mode t r vcc cs 2 t cdr cs 2 0.2v v dd 4.5v 4.5v ws32k32-xhx fig. 6 data retention - cs 2 controlled data retention, cs 2 controlled data retention mode t r vcc cs 2 t cdr cs 2 0.2v v dd 4.5v 4.5v
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs package 9: 32 pin sidebrazed ceramic dip (600 mils wide) all dimensions are in inches pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 package 102: 32 pin sidebrazed ceramic dip (400 mils wide) all dimensions are in inches pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 0.420 0.400 1.616 1.584 0.061 0.017 0.400 nom 0.060 0.040 package 12: 32 pin ceramic quad lcc all dimensions are in inches 0.050 0.040 x 45 0.560 0.458 0.442 0.540 0.120 0.060 0.055 0.045 0.028 0.022 bsc. ref. ref. 0.020 x 45
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs package 142: 32 pin ceramic flatpack all dimensions are in inches pin 1 0.019 0.015 0.040 0.030 0.290 0.270 0.116 0.100 0.050 typ 0.420 0.400 1.00 ref 0.045 0.020 0.007 0.003 0.830 0.810 0.370 0.250 package 140: 32 lead ceramic soj all dimensions are in inches 0.010 0.006 0.050 typ 0.444 0.430 0.840 0.820 0.155 0.106 0.379 0.019 0.015 package 141: 32 pad ceramic lcc all dimensions are in inches 0.096 0.080 0.050 typ 0.405 0.395 0.840 0.820 0.028 0.022
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88130cs ordering information white electronic designs sram organization, 128kx8 (130 = dual cs) technology: cs = cmos standard power (5v) lps = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) f = 32 lead ceramic flatpack (package 142) l = 32 pad ceramic lcc (package 141) l32 = 32 pad ceramic quad lcc (package 12) n = 32 lead ceramic soj (package 140) t = 32 lead sidebrazed dip, 400 mil (package 102) device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 8 130 cs x x x
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